Abstract: In this paper, a low-power high speed 4:2 compressor circuit is proposed for fast digital arithmetic integrated circuits. The 4:2 compressor has been widely employed for multiplier realizations. Based on a new exclusive OR (XOR) and exclusive NOR (XNOR) module, a 4:2 compressor circuit has been designed. Proposed circuit shows power consumption is very less. Power consumption and delay of proposed 4-2 compressor circuit have been compared with earlier reported circuits and proposed circuit is proven to have the minimum power consumption and the lowest delay. Simulations have been performed by using verilog HDL.

Keywords: Full-Adder (FA), XOR-XNOR